Locked loop circuits, such as phase locked loop circuits, are basic components of radio, wireless, and telecommunication technologies. A phase locked loop (PLL) is a control system that generates an output signal having a phase related to the phase of an input signal.
A sample PLL is now described with reference to FIG. 1. The PLL 50 includes a variable frequency oscillator 58 (here, a voltage controller oscillator VCO), a divider 60, a phase frequency detector (PFD) 52, a charge pump 54, and a loop filter 56. The VCO 58 generates a periodic signal Fout, and the divider 60 divides the frequency of the output signal Fout to produce signal Fdiv. The phase frequency detector 52 compares the phase of that signal Fdiv with the phase of a reference periodic signal Fref, and generates the control signals UP, DN for the charge pump 54 based upon that phase comparison. When the phase of the signal Fref leads the phase of the signal Fdiv, the control signal UP is asserted at a logic high, while the control signal DN remains at a logic low and the voltage Vp at the output of the charge pump 54 increases. Conversely, when the phase of the signal Fref lags the phase of the signal Fdiv, the control signal DN is asserted at a logic high, while the control signal UP remains at a logic low and the voltage Vp does not change. When the phase of the signal Fref and the phase of the signal Fdiv match, neither UP nor DN are asserted at a logic high.
The voltage Vp output from the charge pump 54 is used to generate a control signal Vc for the VCO 58, by passing voltage Vp through the loop filter 56, which is typically a low pass filter operating to extract the low frequency content of the voltage Vp. The VCO 58, in response to the control signal, adjusts the phase and frequency of the output signal Fout. When UP is asserted, the voltage of the control signal Vc increases and the frequency of Fout also increases. Conversely, when DN is asserted, the voltage of the control signal Vc decreases and the frequency of Fout also decreases. Since the phase of the signal Fref cannot both lead and lag the phase of the signal Fdiv, the phase frequency detector 52 will not simultaneously assert both UP and DN.
In addition to synchronizing signals, the PLL 50 can track an input frequency, or it can generate a frequency that is a multiple (or fraction) of the input frequency.
Such phase locked loops are widely employed in radio, telecommunications, computers and other electronic applications. They can be used to provide inputs to circuits that demodulate a signal, recover a signal from a noisy communication channel, generate a stable frequency at multiples of an input frequency (frequency synthesis), or distribute precisely timed clock pulses in digital logic circuits such as microprocessors. Since a single integrated circuit can provide a complete phase locked loop building block, phase locked loops are widely used in modern electronic devices, with output frequencies from a fraction of a hertz up to many gigahertz.
In some cases, it may be desirable for a phase locked loop to multiply a relatively low reference frequency Fref, on the order of tens of kilohertz, to a relatively high output frequency Fout, on the order of tens of megahertz. While phase locked loops capable of performing this functionality exist, the time to achieve lock for such phase locked loop circuits is about 1 millisecond, which may be too long or certain applications requiring a fast wake up time.
Therefore, further development work on PLL circuits is needed.